The present invention relates generally to buffering events in a computer system in a memory and accessing this memory in way that provides the maximum mount of information with the fewest accesses.
In a computer system, various events are detected by the hardware and must be subsequently handled by a processor. These events include signals received on inbound Input/Output (I/O) interfaces, power and cooling systems alerts, error conditions, and failure conditions. Sometimes these events can happen faster than they can be handled in real time by the processor. To overcome this, a small memory element is typically added to the system to temporarily store the events until they can be handled by the processor. The memory element is often structured as a first-in, first-out (FIFO) buffer in a communication system.
When the processor is physically and logically located at a distance from the FIFO, each access that the processor makes to read the FIFO takes a considerable amount of time. As processors get faster, the number of processor cycles consumed waiting for the returned FIFO data increases. As this problem has been recognized, other related problems have been experience during development. When the FIFO fills with many events, the processor must access the FIFO for each event in the FIFO. Each time an event is put into the FIFO, the system causes an interrupt to the processor. These events cause considerable overhead to the processor since the processor typically makes a context switch to software used to handle the interrupt.
It has been recognized that it would be desireable to present the maximum information to a processor each time it reads the FIFO buffer in a communication system. This invention presents different information depending on the state of the FIFO (its fullness), and the state of the system. The preferred embodiment for a computer system having a communication link processor and employing a FIFO buffer and controling an asynchronous event storing and recording mechanism to write discreet events into the FIFO at a location determined by a write pointer; and then reading with the attached communication link processor reading the recording mechanism""s FIFO at a location determined by a read pointer. Then the recording mechanism conditionally returns event and status information and conditionally increments the FIFO read pointer.
In accourdance with the preferred embodiment a fullness indication of the FIFO is returned in the read information as the value of the FIFO read pointer and write pointer. Furthermore, the recording mechanism returns system status when the FIFO is completely empty; and an event description when the FIFO has one or more valid entries.
The preferred embodiment of the invention has a mode where the processor can read multiple entries of the FIFO using a single command. Once again, the format of the returned data is different from the variable information returned by a single FIFO access.
It is another object of the present invention to reduce the number of interrupts presented to the processor by sharing information as to the fullness of the FIFO as observed by the processor and known to the FIFO.